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PEDL7662-02
PEDL7662-02 This version: Oct. 1999 MSM7662 Previous version : Oct. 1998
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Semiconductor MSM7662
Semiconductor NTSC/PAL Digital Video Decoder
GENERAL DESCRIPTION
The MSM7662 is an LSI device that decodes NTSC or PAL analog video signals into YCbCr and RGB digital data based on ITU-RBT.601. The device has built-in two channels of A/D converters and can accept composite video and S video signals for the input video signals. Composite video signals are converted to YCbCr and RGB digital data via the 2-dimensional Y/C separation circuit with an adaptive filter. Analog video signals can be sampled by a clock at the pixel frequency or at twice the pixel frequency. A decimation filter is built-in for sampling at twice the pixel frequency. Input signals are synchronized internally and high-speed locking for color burst is possible. Because a FIFO buffer is built into the output format circuit, jitter-free output can be obtained even for non-standard signals.
APPLICATION EXAMPLES
Since the synchronization of input signals and high-speed locking for color burst are possible, the device is optimized for applications used by switching multiple cameras. It is also used for various image processing applications because of jitter-free output data through a built-in FIFO buffer. 8-bit (YCbCr), 16-bit (8-bit (Y) + 8-bit (CbCr)), and 24-bit (RGB) output interfaces can be selected as an output mode so that various devices such as monitoring system, digital video memory, digital TV, video processing unit and video communication unit can be selected on the receiving side.
FEATURES (* new feature not found on MSM7661B)
* Input analog signal NTSC/PAL composite video signal or S-video signal * Maximum 5 composite or 2 S-video + 2 composite analog inputs can be connected (switchable by external pins or internal registers) * Built-in clamp circuits and video amps * Built-in 8-bit A/D converters (2 channels) * 4 selectable output interfaces ITU-RBT.656 (conditional) 8-bit (YCbCr) : 8-bit (YCbCr) YCbCr = 4 : 2 : 2/YCbCr = 4 : 1 : 1 (limit) 16-bit (YCbCr) : 8-bit (Y) + 8-bit (CbCr) YCbCr = 4 : 2 : 2/YCbCr = 4 : 1 : 1 (limit) 24-bit RGB : 8-bit (R) + 8-bit (G) + 8-bit (B) 2-dimensional Y/C separation using adaptive comb filter (this filter is bypassed for S-video signal input) NTSC format: 3 lines or 2 lines, PAL format: 2 lines (3 virtual lines) * Selectable data I/O signal synchronization 4 synchronization modes, internal FIFO modes (FIFO-1, FIFO-2) and external field memory modes (FM-1, FM-2), are selectable (FIFO-1 is normally selected).
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PEDL7662-02 Semiconductor MSM7662
13.5 MHz (13.5/27 MHz) : NTSC/PAL ITU-RBT.601 12.272727 MHz (12.272727/24.545454 MHz) : NTSC Square pixel 14.31818 MHz (14.31818/28.63636 MHz) : NTSC 4fsc 14.75 MHz (14.75/29.5 MHz) : PAL Square Pixel * Built-in AGC/ACC circuits, compatible with a wide range of input levels Input level range: -8 dB to +3.5 dB (0.4 V to 1.5 V) Switchable between AGC/MGC (fixed gain) and ACC/MCC (fixed gain) Decimation filter built into input stage, allows easy configuration of filter prior to A/D converter (when input at twice the pixel frequency) Automatic NTSC/PAL recognition (only for ITU-RBT.601) Sleep mode Multiplex signal recognition (closed caption) During vertical blanking interval, data is output as 8-bit data. I2C-bus interface 3.3 V single power supply (I/O 5 V tolerance) Package: 100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product name: MSM7662TB)
Compatible pixel frequencies (normal/twice the pixel frequency)
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BLOCK DIAGRAM
Semiconductor
CLKX2O INS[2:0] GAINS[2:0] CLKXO
CLKX2 CLKSEL
PLLSEL
VSYNC_L HVALID
VVALID
STATUS1
STATUS3
HSYNC_L
ODD/EVEN
STATUS2
Synchronization Block VRT2 ADIN2 AMPOUT2 CLPOUT2 VRB2 VIN6 VIN5
SW Matrix
M[7:4] M[2:1]
ANALOG AGC& AMP
Decimation Filter Decimation Filter
C ADC
Prologue Block
Luminance Block DIGITAL (AGC or MGC + LPF) Epilogue Block
(2 Dim. Y/C separate) Y ADC Line Memory (1 KB) 2 Chrominance Block (ACC or MCC + LPF)
ITU-656 & 8 bits (YCbCr)
Y[7:0] (G[7:0])
VIN4 VIN3 VIN2 VIN1 VRB1 CLPOUT1 AMPOUT1 ADIN1 VRCL1 VRT1
ANALOG AGC& AMP I2C-bus Control Logic Test Control Logic
Output Formatter
8 bits (Y) 8 bits (CbCr)
C[7:0] (R[7:0])
8 bits (R) 8 bits (G) 8 bits (B)
B[7:0]
PEDL7662-02
MSM7662
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MODE[3:0]
SCL
SDA
RESET_L
SLEEP
SCAN
TEST[2:0]
PEDL7662-02
,
Semiconductor
96 GAINS[0] 95 GAINS[1] 94 GAINS[2] 100 DAGND 99 INS[0] 98 INS[1] 97 INS[2] 92 DGND 93 DVDD
DAVDD VRT2 VIN6 VIN5 1 2 3 4 5 6 7 8 9 ADDD AGND ADIN2 AMPOUT2 CLPOUT2 VRB2 10 AGND 11 AGND 12 VRB1 13 CLPOUT1 14 AMPOUT1 15 ADIN1 16 VRCL1 17 AGND 18 AVDD 19 VIN4 20 VIN3 21 VIN2 22 VIN1 23 VRT1 24 DAVDD 25
MSM7662
PIN CONFIGURATION (TOP VIEW)
83 STATUS1
82 STATUS2
81 STATUS3
77 CLKX2O
76 CLKXO
75 HSYNC_L 74 VSYNC_L 73 VVALID 72 HVALID 71 ODD/EVEN 70 C[0] 69 C[1] 68 C[2] 67 C[3] 66 C[4] 65 C[5] 64 C[6] 63 C[7] 62 DGND 61 DVDD 60 Y[0] 59 Y[1] 58 Y[2] 57 Y[3] 56 Y[4] 55 Y[5] 54 Y[6] 53 Y[7] 52 DVDD 51 DGND
80 CLKX2 B[4] 46
DAGND 26
MODE[0] 27
MODE[1] 28
MODE[2] 29
MODE[3] 30
SCAN 31
TEST[2] 32
TEST[1] 33
TEST[0] 34
SLEEP 35
RESET_L 36
DVDD 37
DGND 38
SCL 39
SDA 40
PLLSEL 41
CLKSEL 42
B[7] 43
B[6] 44
B[5] 45
B[3] 47
B[2] 48
78 DGND
79 DVDD
91 M[0]
90 M[1]
89 M[2]
88 M[3]
87 M[4]
86 M[5]
85 M[6]
84 M[7]
B[1] 49
100-Pin Plastic TQFP
B[0] 50
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PEDL7662-02 Semiconductor MSM7662
PIN DESCRIPTIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Symbol DAVDD VRT2 VIN6 VIN5 AVDD AGND ADIN2 AMPOUT2 CLPOUT2 VRB2 AGND AGND VRB1 CLPOUT1 AMPOUT1 ADIN1 VRCL1 AGND AVDD VIN4 VIN3 VIN2 VIN1 VRT1 DAVDD DAGND Type -- O I I -- -- I O O O -- -- I O O I I -- -- I I I I O -- -- Description Digital power supply in A/D converter A/D converter reference voltage (high side) for S-video chroma signal S-video 2 chroma signal (C-2) input pin (leave open or connect to AGND when not used) Composite-5 or S-video 1 chroma signal (C-1) input pin (leave open or connect to AGND when not used) Analog power supply Analog ground A/D converter input pin for S-video chroma signal S-video chroma signal amp output S-video chroma signal clamp voltage output A/D converter reference voltage (low side) for S-video chroma signal Analog ground Analog ground A/D converter reference voltage (low side) for composite/S-video (luminance signal) Composite/S-video (luminance signal) clamp voltage output Composite/S-video (luminance signal) amp output A/D converter input pin for composite/S-video (luminance signal) S-video (luminance signal) clamp voltage input Analog ground Analog power supply Composite-4 input (leave open or connect to AGND when not used) Composite-3 input (leave open or connect to AGND when not used) Composite-2 S-video 2 luminance signal (Y-2) input (leave open or connect to AGND when not used) Composite-1 S-video 1 luminance signal (Y-1) input (leave open or connect to AGND when not used) A/D converter reference voltage (high side) for composite/S-video (luminance signal) Digital power supply in A/D converter Digital ground in A/D converter
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PEDL7662-02 Semiconductor MSM7662
PIN DESCRIPTIONS (continued)
Pin 27 28 29 30 Symbol MODE[0] MODE[1] MODE[2] MODE[3] Type I I I I Description I/O switching input during external setting mode (pulled-down by internal resistors) Internal/external pins are switched by register MRA[0] The default of register MRA[0] is external pin mode. MODE [3:2] Output mode selection 00: ITU-RBT.656 (with 8-bit YCbCr SAV, EAV, blank processing) 01: 8-bit (YCbCr) 10: 16-bit (YCbCr) (ITU-RBT.601) 11: 24-bit RGB MODE [1] Input mode selection 0: NTSC 1: PAL Invalid if an ITU-RBT.601 signal is input while the register MRC[7] is set to automatic NTSC/PAL recognition. MODE [0] Input mode selection 0: ITU-RBT.601 1: Square Pixel NTSC 4fsc can be set by register MRA [3:1] only. 31 32 33 34 35 36 37 38 39 40 41 42 SCAN TEST[2] TEST[1] TEST[0] SLEEP RESET_L DVDD DGND SCL SDA PLLSEL CLKSEL I I I I I I -- -- I I/O I I Not used. Be left open or fixed at "0" (pulled down by internal resistor). Not used. Be left open or fixed at "0" (pulled down by internal resistor). Not used. Be left open or fixed at "0" (pulled down by internal resistor). Not used. Be left open or fixed at "0" (pulled down by internal resistor). 0: normal operation, 1: sleep operation Reset input pin (active "L"). After powering ON, be sure to reset. Digital power supply Digital ground I2C-bus clock input I2C-bus data I/O pin Not used. Be left open or fixed at "0" (pulled down by internal resistor). Clock select input pin (pulled down by internal resistor). 0: double-speed input mode Data output 43 to 50 B[7] to B[0] O 1: normal input mode When a double-speed input mode is used, input a double frequency to system clock. B[7]: MSB, B[0]: LSB During RGB output mode: B 8-bit data output Other than RGB output mode: Hi-Z Output mode is set by pin 27 or 28, or register MRA [7:6]. 51 52 DGND DVDD -- -- Digital ground Digital power supply
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PEDL7662-02 Semiconductor MSM7662
PIN DESCRIPTIONS (continued)
Pin Symbol Type Data output Description Y[7]: MSB, Y[0]: LSB During ITU-RBT.656 output mode: YCbCr 8-bit data output 53 to 60 Y[7] to Y[0] O During 8-bit (YCbCr) output mode: YCbCr 8-bit data output During 16-bit (YCbCr) output mode: Y 8-bit data output During 24-bit RGB output mode: G 8-bit data output Output mode is set by pin 27 or 28, or register MRA [7:6]. 61 62 DVDD DGND -- -- Digital power supply Digital ground Data output C[7]: MSB, C[0]: LSB During ITU-RBT.656 output mode: Hi-Z 63 to 70 C[7] to C[0] O During 8-bit (YCbCr) output mode: Hi-Z During 16-bit (YCbCr) output mode: CbCr 8-bit data output During 24-bit RGB output mode: R 8-bit data output Output mode is set by pin 27 or 28, or register MRA [7:6]. 71 72 73 74 75 ODD/EVEN HVALID VVALID VSYNC_L HSYNC_L O O O O O Field display output If field is odd, "H" is output. Horizontal valid pixel timing output pin If section is valid, "H" is output. Vertical valid line timing output pin If section is valid, "H" is output. Vertical sync signal (V sync) output pin Horizontal sync signal (H sync) output pin Pixel clock output During double-speed input mode (pin 42 = 0): One half of system clock 76 CLKXO O frequency is output. During normal input mode (pin 42 = 1): The same frequency as system clock frequency is output. 77 78 79 CLKX2O DGND DVDD O -- -- System clock output System clock input is directly output. Digital ground Digital power supply System clock input (selected by operation mode) Normal input mode NTSC ITU-RBT.601 80 CLKX2 I NTSC Square Pixel NTSC 4fsc PAL ITU-RBT.601 PAL Square Pixel 13.5 MHz 12.272727 MHz 14.31818 MHz 13.5 MHz 14.75 MHz Double-speed input mode 27 MHz 24.545454 MHz 28.63636 MHz 27 MHz 29.5 MHz
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PEDL7662-02 Semiconductor MSM7662
PIN DESCRIPTIONS (continued)
Pin Symbol Type Status signal output Selected by internal register OMR[0] 81 STATUS[3] O OMR[0]: 0 OMR[0]: 1 FIFO overflow detection (default) 0: non-detection, 1: detection CSYNC output Status signal output Selected by internal register OMR[1] 82 STATUS[2] O OMR[1]: 0 OMR[1]: 1 NTSC-PAL recognition (default) 0: NTSC, 1: PAL HLOCK sync detection output 0: non-detection, 1: detection 83 84 85 86 87 88 89 STATUS[1] M[7] M[6] M[5] M[4] M[3] M[2] O O O O O O I VBI interval multiplex signal detection output 0: non-detection, 1: detection Field memory control signal; RE output Field memory control signal; WE output Field memory control signal; RSTR output Field memory control signal; RSTW output Test output pin, normally "L" output I2C-bus slave address select 0: 1000001X 1: 1000011X (no internal pull-up or pull-down resistor) Pin for setting by either external pin or internal register in order to select analog unit gain value (MGC) and video signal input pin. (no internal pull-up or pull-down resistor) 0: external pin mode 90 M[1] I Gain value setting: pins 94 to 96 (GAINS[2:0]) are used Input pin setting: pins 97 to 99 (INS[2:0]) are used 1: register mode Gain value setting: register ADC2[6:4] Input pin setting: register ADC1[2:0] Internal register setting is invalid when external pin mode is set. Selection of external field memory control signal output 91 M[0] I If field memory is not used, set M[0] to 0. 0: M[7:4] outputs are invalid 1: M[7:4] outputs are valid 92 93 DGND DVDD -- -- Digital ground Digital power supply Description
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PEDL7662-02 Semiconductor MSM7662
PIN DESCRIPTIONS (continued)
Pin 94 95 96 Symbol GAINS[2] GAINS[1] GAINS[0] Type I I I Description Inputs for amplifier gain switch setting during external setting mode External pin mode: pin 90 (M[1]) = 0 (pulled down by internal resistors) GAINS[2:0] [000] [001] [010] [011] [100] [101] [110] [111] 97 98 99 INS[2] INS[1] INS[0] I I I Gain value (x times) 1.00 1.35 1.75 2.30 3.00 3.80 5.00 Undefined
Inputs for signal input pin switch setting during external setting mode External pin mode: pin 90 (M[1]) = 0 (pulled down by internal resistors) INS[2:0] [000] [001] [010] [011] [100] [101] [110] [111] Input pin VIN1 (pin 23) Composite-1 VIN2 (pin 22) Composite-2 VIN3 (pin 21) Composite-3 VIN4 (pin 20) Composite-4 VIN5 (pin 4) Composite-5 VIN1 (pin 23) Y-1 VIN5 (pin 4) C-1 VIN2 (pin 22) Y-2 VIN6 (pin 3) C-2 Prohibited setting (ADC enters sleep state)
100
DAGND
--
Digital ground in A/D converter
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PEDL7662-02 Semiconductor MSM7662
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage Power Consumption Storage Temperature Symbol VDD VI PW TSTG Condition Ta = 25C VDD = 3.3 V -- -- Rating -0.3 to +4.5 -0.3 to +5.5 1 -55 to +150 Unit V V W C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Power Supply Voltage Digital "H" Level Input Voltage Digital "L" Level Input Voltage Analog Video Signal Input Operating Temperature Symbol VDD GND VIH1 VIH2 (*1) VIL VAIN Ta Condition -- -- -- -- -- SYNC tip to white peak level -- Min. 3.0 -- 2.2 0.8 VDD 0 0.8 0 Typ. 3.3 0 -- -- -- -- -- Max. 3.6 -- VDD (*2) VDD (*2) 0.8 1.1 70 Unit V V V V V VP-P C
*1: *2:
CLKSEL, SDA, CLKXO Since the inputs have a tolerance of up to 5.5 V, it is possible to apply 5 V to the inputs.
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PEDL7662-02 Semiconductor MSM7662
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta = 0 to 70C, VDD (DVDD, ADVDD, AVDD) = 3.3 V 0.3 V) Parameter "H" Level Output Voltage "L" Level Output Voltage Symbol VOH VOL Condition IOH = -4 mA (*1) IOH = -6 mA (*2) IOL= 4 mA (*1) IOL= 6 mA (*2) VI = GND to VDD Input Leakage Current Output Leakage Current SDA Output Voltage SDA Output Current II IO SDAVL SDAIO Rpull_down = 50 kW (*3) VI = GND to VDD -- -- Min. 0.7 VDD 0 -10 20 -10 0 3 Typ. -- -- -- -- -- -- -- Max. VDD 0.4 +10 250 +10 0.4 -- Unit V V mA mA mA V mA
*1: *2: *3:
HSYNC_L, VSYNC_L, SYSSEL, C[7:0], B[7:0], ODD, VVALID, HVALID, CLKXO, HSY, M[7:0] Y[7:0], CLKX2O MODE[3:0], SCAN, TEST[2:0], PLLSEL, CLKSEL, GAINS[2:0], INS[2:0]
DC Characteristics (Analog Unit)
(Ta = 0 to 70C, VDD (DVDD, ADVDD, AVDD) = 3.3 V 0.3 V, GND = 0 V) Parameter AMPOUT Output Voltage CLPOUT Output Voltage VRT Output Voltage VRB Output Voltage ADIN VIN Input Current Symbol VOAMP VOCLP VRT VRB VIADIN VIVIN IIVIN Condition RO = 300 W RO = 5 kW (*) (*) -- Capacitive coupling VI = 1.5 V Min. 0.3 0.2 2.0 0.15 VRB 0.4 5 Typ. -- -- 2.3 0.3 -- -- -- Max. 2.4 1.6 2.4 0.4 VRT 1.3 30 Unit V V V V V VP-P mA
*:
10 kW connected between VRT and VRB
DC Characteristics
(Ta = 0 to 70C, VDD (DVDD, ADVDD, AVDD) = 3.3 V 0.3 V, GND = 0 V) Parameter Power Supply Current (Operating) Symbol ID1 Condition AD1 on AD2 off CLKX2 = 27 MHz AD1 on Power Supply Current (Operating) Power Supply Current (Sleep) ID2 IDOFF AD2 on CLKX2 = 27 MHz VI = 1.5 V 0 5 mA 140 170 240 mA 120 150 210 mA Min. Typ. Max. Unit
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PEDL7662-02 Semiconductor AC Characteristics (Double Speed Mode)
(Ta = 0 to 70C, VDD (DVDD, ADVDD, AVDD) = 3.3 V 0.3 V, GND = 0 V) Parameter Symbol Condition ITU-RS601 CLKX2 Cycle Frequency 1/tCLKX2 NTSC 4fsc NTSC Square Pixel PAL Square Pixel CLKX2 Duty Output Data Delay Time 1 (*) Output Data Delay Time 2 (*) Output Data Delay Time 3 (*) Output Data Delay Time 1X1 (*) Output Data Delay Time 1X2 (*) Output Data Delay Time 1X3 (*) Output Data Delay Time 2X1 (*) Output Data Delay Time 2X2 (*) Output Data Delay Time 2X3 (*) Output Clock Delay Time (*) (CLKX2-CLKXO) Output Clock Delay Time (*) (CLKX2-CLKX2O) SCL Clock Cycle Time SCL Low Level Cycle RESET_L Width tD_D2 tOD21 tOD22 tOD23 tODX21 tODX22 tODX23 tOD2X21 tOD2X22 tOD2X23 tCXD21 tCXD22 tC_SCL tL_SCL tRST_W -- CLKSEL : L CLKSEL : L CLKSEL : L CLKSEL : L CLKSEL : L CLKSEL : L CLKSEL : L CLKSEL : L CLKSEL : L CLKSEL : L CLKSEL : L Rpull_up = 4.7 kW Rpull_up = 4.7 kW Min. -- -- -- -- 45 7 (5) 6 (4) 7 (5) 2 1 2 3 (1) 2 (1) 3 (1) 5 4 200 100 200 Typ. 27.0 28.63636 24.545454 29.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- -- 55 26 (24) 22 (20) 30 (28) 8 5 10 11 (9) 9 (7) 13 (11) 20 17 -- -- -- Unit MHz MHz MHz MHz % ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MSM7662
(*) Output load: 40 pF Values in the parentheses indicate the delay time when 8-bit YCbCr format data is output from the Y pin. The clock frequency accuracy is within 100 ppm.
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PEDL7662-02 Semiconductor AC Characteristics (Single Speed Mode)
(Ta = 0 to 70C, VDD (DVDD, ADVDD, AVDD) = 3.3 V 0.3 V, GND = 0 V) Parameter Symbol Condition ITU-RS601 CLKX2 Cycle Frequency 1/tCLKX2 NTSC 4fsc NTSC Square Pixel PAL Square Pixel CLKX2 Duty Output Data Delay Time 1 (*) Output Data Delay Time 2 (*) Output Data Delay Time 3 (*) Output Data Delay Time 1X1 (*) Output Data Delay Time 1X2 (*) Output Data Delay Time 1X3 (*) Output Data Delay Time 2X1 (*) Output Data Delay Time 2X2 (*) Output Data Delay Time 2X3 (*) Output Clock Delay Time (*) (CLKX2-CLKXO) Output Clock Delay Time (*) (CLKX2-CLKX2O) SCL Clock Cycle Time SCL Low Level Cycle RESET_L Width tD_D1 tOD11 tOD12 tOD13 tODX11 tODX12 tODX13 tOD2X11 tOD2X12 tOD2X13 tCXD11 tCXD12 tC_SCL tL_SCL tRST_W CLKSEL : H CLKSEL : H CLKSEL : H CLKSEL : H CLKSEL : H CLKSEL : H CLKSEL : H CLKSEL : H CLKSEL : H CLKSEL : H CLKSEL : H CLKSEL : H Rpull_up = 4.7 kW Rpull_up = 4.7 kW Min. -- -- -- -- 40 8 7 8 2 1 2 3 2 3 6 5 200 100 200 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ. 13.5 14.31818 12.272727 14.75 Max. -- -- -- -- 60 26 22 30 8 5 12 11 8 15 20 17 -- -- -- Unit MHz MHz MHz MHz % ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MSM7662
(*) Output load: 40 pF The clock frequency accuracy is within 100 ppm.
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PEDL7662-02 Semiconductor MSM7662
INPUT AND OUTPUT TIMING
Clock and Output Timing
CLKSEL: H tCLKX1 CLKSEL: L tCLKX2
CLKX2 tCXD21 CLKX2O tCXD11 CLKXO tOD11 tOD2X11 tODX11 tOD12 tOD2X12 HVALID, VVALID, ODD HSYNC_L, VSYNC_L tODX12 tOD13 tOD2X13 tODX13 tCXD21 tOD21 tOD2X21 tODX21 tOD22 tOD2X22 tODX22 tOD23 tOD2X23 tODX23 tCXD22
Y[7:0], C[7:0] B[7:0]
STATUS[3:1] M[7:4]
Data Delay (when a standard signal is input)
Analog Video In Data delay Blank delay Decoder output Blank Active Data
T = 1 pixel rate, a = absorption difference Video Mode NTSC NTSC PAL PAL NTSC, PAL NTSC, PAL Input Signal Composite Composite Composite Composite S-Video S-Video FIFO/FM Mode FIFO-1 FM FIFO-1 FM FIFO-1 FM Amount of Delay 1H + 358T a 1H + 358T 1H + 358T a 1H + 358T 358T a 358T
The data delay is equal to the blank delay. 1H depends on the sampling mode. The numeric value (T value) may be changed according to a signal state. Since the output period is fixed during FIFO mode, the amount of delay is changed. If Y/C separation is performed using TRAP filter during PAL mode, 1H is not added. 14/62
PEDL7662-02 Semiconductor I2C-bus Interface Input/Output Timing The basic input/output timing of the I2C-bus is indicated below. MSM7662
SDA SCL
MSB
S Start condition
1
2
7
8
9 ACK
1 tC_SCL
2 3-8
9 ACK
P Stop condition
Data line stable: data valid
Change of data allowed
I2C-bus Timing
SDA tBFU SCL P S tHD:STA tLOW tHD:DAT tHIGH tSU:DAT tSU:STA tSU:STO tR tF S tHD:STA P
Symbol fSCL tBUF tHD: STA tLOW tHIGH tSU: STA tHD: DAT tSU: DAT tR tF tSU: STO SCL Frequency Bus Open Period
Parameter
Min. 0 4.7 4.0 4.7 4.0 4.7 300 250
Max. 100
Unit kHz ms ms ms ms ms ns ns
Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time Data Hold Time Data Setup Time Line Rise Time Line Fall Time Stop Condition Setup Time
1 300 4.7
ms ns ms
The I2C-bus timing conforms to this table. However, the I2C-bus can operate faster than at the speeds, specified above. Actually, the SCL frequency is up to about 5 MHz. The hold time and setup time in that case must conform to the ratio described in the above table.
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PEDL7662-02 Semiconductor MSM7662
FUNCTIONAL DESCRIPTION
Analog Unit 1) Analog input select: Compatible with composite video signals and S-video signals. Input selection can be switched by register control via the I2C-bus or by external pins. (See the below chart for pin combinations.) 2) Clamp function: An analog clamp and a digital pulse clamp can be used. Analog clamp Analog clamp AE Digital clamp (hybrid clamp) Digital clamp Only the digital clamp can be set as the pedestal clamp. # Related register MRB[3:2] 3) AGC amp: The AGC function operates depending upon the input level. Manual gain setting is also possible. This AGC function operates at 2 stages, the analog unit and digital unit. Digital decoded data is output in conformance with ITU-RBT.601. Refer to the explanation of M[1] pin (pin 90). # Related register ADC2[6:4] 4) A/D converter: Two internal 8-bit A/D converters sample at twice the pixel frequency. (Sampling at the pixel frequency is possible by changing the register setting.) # Related register ADC1[2:0] List of Analog Input Conditions
Input Signal Composite-1 Input* Composite-2 Input Composite-3 Input Composite-4 Input Composite-5 Input S-video-1 Input S-video-2 Input All inputs Off Control Pin Register INS[2:0] ADC1[2:0] VIN1 [000] [001] [010] [011] [100] [101] [110] [111] [000] [001] [010] [011] [100] [101] [110] [111] Luminance Luminance OFF (Sleep) Composite Composite Composite Composite Composite Chroma Chroma VIN2 Input Pin VIN3 VIN4 VIN5 VIN6 ADC Selection ON ON ON ON ON ON ON ON OFF OFF OFF OFF OFF OFF OFF ON ON OFF
Blank spaces: non-selectable *: register default setting after LSI reset M[1] pin setting 0: external mode, 1 internal register mode
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PEDL7662-02 Semiconductor Manual Gain Control (analog AMP gain)
Gain Setting Pins GAINS[2:0] [000] [001] [010] [011] [100] [101] [110] [111] Register ADC2[6:4] [000] [001] [010] [011] [100] [101] [110] [111] Set Gain Value Typ. Value (multiplication factor) 1.0 1.35 1.75 2.3 3.0 3.8 5.0 Undefined
MSM7662
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PEDL7662-02 Semiconductor Decoder Unit 1. Prologue Block The prologue block inputs data and performs Y/C separation. Data can be input at either the pixel frequency (ITU-RBT.601: 13.5 MHz) or at twice the pixel frequency (ITU-RBT.601: 27 MHz). If input at twice the pixel frequency, data is processed after passing through a decimator circuit to convert it to the pixel frequency. The decimator circuit may be bypassed by changing the register setting, regardless of whether data is input at the normal pixel frequency or at twice the pixel frequency. If a composite signal (CVBS) is input, the default setting performs Y/C separation using a 2dimensional adaptive comb filter. The following operating modes can be selected via the I2C-bus. Default settings are indicated by an asterisk (*). The default state is selected at reset. 1) Video input mode selection (related register MRC[7]) NTSC/PAL auto-select* (only for ITU-RBT.601) Dependent upon operating mode selected When ITU-RBT.601 is selected, the video input mode is automatically set depending upon the number of lines per field. 2) Operating mode selection (related register MRA[3:1]) NTSC ITU-RBT.601 13.5 MHz* NTSC Square Pixel 12.272727 MHz NTSC 4fsc 14.31818 MHz PAL ITU-RBT.601 13.5 MHz PAL Square Pixel 14.75 MHz Even if input at twice the pixel frequency, the internal processing is performed at the pixel frequency. 3) Decimator circuit pass/bypass selection (related register MRC[4]) Pass through decimator circuit* Bypass decimator circuit Compatible only when input at twice the pixel frequency. 4) Y/C separation mode selection (related register MRB[1:0]) Use adaptive comb filter* Use non-adaptive comb filter Do not use comb filter (use trap filter) The adaptive comb filter for a NTSC signal makes the correlation between up to 3 consecutive lines, and Y/C separation is performed by the 3-line or 2-line comb filter according to the format of correlation. The adaptive comb filter for a PAL signal makes the correlation between only 2 lines and performs Y/C separation by switching between the 2-line comb filter and trap filter. The non-adaptive comb filter performs Y/C separation by removing the luminance component based on the average of preceding and following lines (when there is correlation between 3 lines). (the average of 2 lines in the case of a PAL signal) When a comb filter is not used, Y/C separation is performed by a trap filter. MSM7662
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PEDL7662-02 Semiconductor If an S-video signal is input, these Y/C separation circuits are bypassed. The functions of this block only operate when lines are valid as image information. During the V blanking interval, CVBS signals are not processed. 2. Luminance Block The luminance block removes synchronous signals from signals containing luminance components after Y/C separation. The signals are compensated and then output as luminance signals. Two modes of gain control functions can be selected for the luminance signal output level: AGC (Auto Gain Control) and MGC + Pedestal Clamp. In the AGC mode, luminance level amplification is determined by comparing the SYNC depth with a reference value. The default is 40IRE and can be changed by the register setting. The input has a sync tip clamp. In the MGC + Pedestal Clamp mode, the signal output level is clamped to the pedestal level of the input. Signal amplification and black level can be changed from the clamped position by register settings. This block can select the follwing operating modes. 1) Selection of luminance level limiter usage (related register LUMC[7]) Do not use* Use When a limiter is used, the luminance level is limited to 16 to 235. 2) Selection of prefilter and sharp filter usage (related register LUMC[6]) Do not use* Use These filters are used to enhance the edges of luminance component signals. Two filters operate in pairs. For their characteristics, refer to Filter Characteristics described later. 3) Selection of aperture bandpass filter coefficient (related register LUMC[5:4]) Middle range* High range 4) Coring range selection (related register LUMC[3:2]) Off* 4LBS 5LBS 7LBS 5) Aperture weighting coefficient selection (related register LUMC[1:0]) 0* 0.25 0.75 1.50 Both coring and aperture compensation processes perform contour compensation. 6) Selection of pixel position compensating circuit usage (related register MRC[6]) Use* Do not use MSM7662
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PEDL7662-02 Semiconductor MSM7662
7) AGC loop filter time constant selection (related register AGCLF[7:6]) Slow convergence time 903 ms Medium 225 ms* Fast 56 ms Fixed 0 These are designed times from the input gain being rapidly lowered to 50% (-6 dB) of the value at a stable state when normal signals are input till the output being returned to -1 dB (actually these times differ depending on the signal state). Fixed: manual gain setting is possible by register AGCLF[5:0] 8) Parameter for fine adjustment of AGC sync depth (related register AGCLF[5:0]) AGC reference level is changed. 9) Parameter for fine adjustment of sync removal level (related register SSEPL[6:0]) The black level is adjusted. The default setting outputs the pedestal position as a black level (=16). 10)Pedestal clamp selection (related register SSEPL[7]) Do not use pedestal clamp* Use pedestal clamp (at this time, AGC does not operate, MGC operates) 3. Chrominance Block This block processes the chroma signals. The following operating modes can be selected. 1) Selection of chroma bandpass filter usage (related register CHRC[2]) Do not use* Use 2) ACC loop filter time constant selection (related register ACCLF[6:5]) Slow convergence time 1696 ms Medium 424 ms* Fast 106 ms Fixed 0 These are designed times from the input gain being rapidly lowered to 50% (-6 dB) of the value at a stable state when normal signals are input till the output being returned to -1 dB (actually these times differ depending on the signal state). Fixed: manual gain setting is possible by register ACCLF[4:0] 3) ACC reference level fine adjustment (related register ACCLF[4:0]) ACC reference level is changed. 4) Parameter for burst level fine adjustment (related register CHRC[1:0]) Threshold level at which chroma amplitude becomes valid is selected based upon color burst ratio. 0.5 0.25* 0.125 Off Off: The color killer function is turned off. If decoloration occurs while decoding a still picture, setting the threshold level to "off" will reduce the decoloration. 5) Color killer mode selection (related register MRB[5]) Auto color killer mode* Forced color killer 6) Parameter for fine adjustment of color subcarrier phase (related register HUE[7:0]) HUE control function 20/62
PEDL7662-02 Semiconductor MSM7662
In this block, chroma signals pass through a bandpass filter to cut out unnecessary band. To maintain a constant chroma level, these signals then pass through an ACC compensating circuit and are UV demodulated. (The filter can be bypassed.) If the demodulated result does not reach a constant level, color killer signals are generated to fix the ACC gain. This functions as an auto color killer control circuit. The UV demodulated results pass through a low-pass filter and are output as chrominance signals. 4. Synchronization Block This block processes the sync signals. Synchronous signals are generated for chip output and for internal use. Various signals are output from this block and the following operating modes can be selected. 1) Adjustment of SYNC threshold level (internal sync) (related register STHR[7:0]) SYNC detection level is set. 2) Fine adjustment of HSY (Horizontal Sync Clamp) signal (related registers HSYT[7:4], HSYT[3:0], MRB[3:2]) 2-1) Fine adjustment of HSY signal (start side) 2-2) Fine adjustment of HSY signal (stop side) The HSY signal provides the sync-tip and clamp timing to the A/D converter. This signal is used for digital clamp, but can not be observed from outside. 3) Fine adjustment of HSYNC_L signal (related register HSDL[7:0]) HSYNC_L signal output position is adjusted. 4) HVALID control (related registers HVALT[7:4], HVALT[3:0]) 4-1) Fine adjustment of HVALID signal (start side) 4-2) Fine adjustment of HVALID signal (stop side) Data signals are transferred at the rising edge of the HVALID signal. 5) VVALID control (related registers VVALT[7:4], VVALT[3:0]) 5-1) Fine adjustment of VVALID signal (start side) 5-2) Fine adjustment of VVALID signal (stop side) 6) FIFO and Field Memory mode selection (related register MRB[7:6]) FIFO-1 mode*: Sets and outputs a standard value for the number of pixels per 1H from the internal FIFO. This mode is also compatible (to a degree) with non-standard VTR signals. FIFO-2 mode: Sets and outputs a constant pixel number corresponding to the input H interval for the number of pixels per 1H from the internal FIFO. FM-1 mode: This mode outputs the decoded results according to the SYNC signal. Usage of external field memory is required to manage the number of pixels and to absorb jitter. Memory control signals are to be generated externally. FM-2 mode: This mode is compatible with considerably distorted non-standard VTR signals. Jitter is absorbed by using external field memory (2 Mb 2) and the standard value is set as the pixel number. Field memory control signals are output simultaneously from M[7:4]. 7) Field memory control signals If the FM-2 mode uses external field memory (2 Mb 2) instead of the internal FIFO, field memory control signals are supplied from pins M[7:4]. At this time, pin M[0] requires to be set to "H".
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PEDL7662-02 Semiconductor 5. Epilogue Block The Epilogue Block outputs the UV signal from the Chrominance block and the Y signal from the Luminance block in a format based on a signal obtained from the control register setting. This block can select the following modes. 1) Output mode selection (related register MRA[7:6]) 1-1) ITU-RBT.656 (SAV, EAV, blank processing) 1-2) * 8-bit (YCbCr) output (2x pixel clock) synchronization with HSYNC_L, VSYNC_L 1-3) 16-bit (8-bit Y/8-bit CbCr) (pixel clock) synchronization with HSYNC_L, VSYNC_L 1-4) 24-bit RGB (8 bits each) synchronization with HSYNC_L, VSYNC_L 2) Enable Blue Back display when synchronization fails (related register MRB[4]) OFF ON* If "H" is not input when no signal is output or when synchronization fails, a vertical synchronizing signal (VSYNC_L) is not output. 3) Selection of YCbCr signal output format (related register MRC[5]) YCbCr 4 : 2 : 2* YCbCr 4:1:1 The chrominance signal (U, V component) outputs Cb and Cr data to the C pin in an output format to be described later. 4) Output pin enable selection (related register OMR[2]) High-impedance Output enable* This setting is valid during sleep mode only. All the data output pins and sync signal output pins become high impedance. 5) Multiplex signal (VBI data) detection level adjustment (related register OMR[5:3]) The levels to detect multiplexed signals sent during the vertical blanking period are configured to be variable. The binary values after input signals are A-to-D converted are employed as the levels to detect multiplexed signals, and the levels are set in eight steps on the basis of a value obtained from reducing the SYNC tip level to 0. 6) Various mode detection (related register OMR[1:0]) NTSC/PAL detection Multiplex signal detection HSYNC synchronization detection Internal FIFO overflow detection 7) Output signal phase control (related registers OPCY[1:0], OPCC[1:0]) Y and C phases can each be adjusted in the range of -2 to +1 pixels. 6. I2C Control Block This serial interface block is based on the I2C standard of the Phillips Corporation. The registers at up to subaddress Hex14 are write-only registers and the register at subaddress Hex20 is a read-only register. The license to use the LSI chip for I2C systems is granted on the basis of the I2C patent of the Phillips Corporation by purchasing the LSI chip. 7. Test Control Block This block is used to test the LSI chip. Normally this block is not used. MSM7662
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PEDL7662-02 Semiconductor Input Signal Level The figure below shows the recommended range of the input signal, received in an 8-bit straight binary format.
255 reserved 246 200
MSM7662
Iuminance
chrominance +DC
NTSC:60 (PAL:63) sync 4 0
input black level 13 input sync-tip level CVBS[7:0] input range
The above input conditions are ideal. Because analog signals are normally input at different levels, the exact settings described above are difficult to achieve. While maintaining the ratio of White Peak (100%)/SYNC = 100IRE/40IRE (NTSC), if the input signal is set within the A/D converter's voltage range/the Y digital output will be output by digital AGC operation with the pedestal position set at the black level (16) and the white peak position (100%) set at the peak level (235) even if the peak level does not reach 196 (200 - 4).
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PEDL7662-02 Semiconductor Output format ITU-RBT.656 output, 8-bit (YCbCr) output, and 16-bit (8-bit Y/8-bit CbCr) output have the following formats. The YCbCr 4:2:2 format and 4:1:1 format are shown below. The output format can be changed by register settings.
Output Y7 (MSB) Y6 Y5 Y4 Y3 Y2 Y1 Y0 (LSB) C7 (MSB) C6 C5 C4 C3 C2 C1 C0 (LSB) Y point C point Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb0 0 0 Pixel Byte Sequence Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0 1 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb0 2 2 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0 3 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb0 4 4 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0 5 Output Y7 (MSB) Y6 Y5 Y4 Y3 Y2 Y1 Y0 (LSB) C7 (MSB) C6 C5 C4 C3 C2 C1 C0 (LSB) Y point C point Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7 Cb6 Cr7 Cr6 0 0 0 0 0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb5 Cb4 Cr5 Cr4 0 0 0 0 1 0 YCbCr 4:1:1 format Pixel Byte Sequence Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb3 Cb2 Cr3 Cr2 0 0 0 0 2 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb1 Cb0 Cr1 Cr0 0 0 0 0 3 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7 Cb6 Cr7 Cr6 0 0 0 0 4 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb5 Cb4 Cr5 Cr4 0 0 0 0 5 4 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb3 Cb2 Cr3 Cr2 0 0 0 0 6 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb1 Cb0 Cr1 Cr0 0 0 0 0 7
MSM7662
YCbCr 4:2:2 format
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PEDL7662-02 Semiconductor MSM7662
TIMING DESCRIPTION
Vertical Synchronizing Signal The vertical synchronizing signal timing is as follows. The default output is as shown below, but the internal processing of the synchronizing signal is performed before 1H.
524 CVBS HVALID HSYNC_L VSYNC_L CSYNC_L VVALID ODD 262 CVBS HVALID HSYNC_L VSYNC_L CSYNC_L VVALID ODD 263 264 265 266 267 268 269 270 271 283 284 285 525 1 2 3 4 5 6 7 8 9 21 22
Vertical Synchronizing Signal (60 Hz)
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PEDL7662-02 Semiconductor MSM7662
621 CVBS HVALID HSYNC_L CSYNC_L VSYNC_L VVALID ODD 309 CVBS HVALID HSYNC_L CSYNC_L VSYNC_L VVALID ODD
622
623
624
625
1
2
3
4
5
6
23
24
310
311
312
313
314
315
316
317
318
336
337
338
Vertical Synchronizing Signal (50 Hz)
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PEDL7662-02 Semiconductor A/D Converter Support Signal The waveform of the HSY signal, shown below, provides clamp timing to the A/D converter when HSY clamp (digital clamp) is selected. The start and end edges of the clamp pulse have a variable range from the sync tip to the pedestal position. (HSY is an internal signal.) MSM7662
CVBS BURST
COLOR BURST
sync tip HSY
Pedestal
A/D Converter Support Signal Output Timing * ITU-RBT.656 output
T : clock periods 37 ns normal (1/27 MHz) SAV : start of active video timing reference code EAV : end of active video timing reference code Digital line {1716T (NTSC, 525), 1728T (PAL, 625)} Multiplexed video data Cb0 Y00 Cr0 Cb1 Y10 Cr1 Y11 4T Digital active line Video data block (1440T)
SAV EAV EAV
4T Digital line blanking 276T (NTSC, 525) 288T (PAL, 625)
ITU-RBT.656 Output (Data in one line in which video data presents) During the blanking interval, data is output with the Y value. Note: Digital line 1716T (NTSC, 525) and 1728T (PAL, 625) are not maintained at the next line. Digital active line 1440T of the line immediately after VVALID falls and the 10th or 11th line after VSYNC_L rises will fluctuate due to pixel compensation. Especially when a non-standard signal is input, the line immediately after VVALID falls will fluctuate largely due to instability of the input signal. Due to phenomena such as an increase in the number of lines for a standard signal and a decrease in the number of lines for a nonstandard signal, it may not be possible to guarantee correct EAV and SAV functionality. 27/62
PEDL7662-02 Semiconductor Contents of SAV and EAV Both SAV and EAV consist of 4 words. Their configuration is shown below.
Word First Second Third Fourth Bit No. 7 (MSB) 1 0 0 1 6 1 0 0 F 5 1 0 0 V 4 1 0 0 H 3 1 0 0 P3 2 1 0 0 P2 1 1 0 0 P1 0 (LSB) 1 0 0 P0 F = 0: during field 1 1: during field 2 V = 0: elsewhere 1: during field blanking H = 0: SAV H = 1: EAV P3, P2, P1, P0: Protection bit
MSM7662
The 4th word of SAV and EAV The relationship between the F, V, H and Protection bits in the 4th word of SAV and EAV is shown below.
Bit No. Function 0 1 2 3 4 5 6 7 7 (MSB) Fixed 1 1 1 1 1 1 1 1 1 6 F 0 0 0 0 1 1 1 1 5 V 0 0 1 1 0 0 1 1 4 H 0 1 0 1 0 1 0 1 3 P3 0 1 1 0 0 1 1 0 2 P2 0 1 0 1 1 0 1 0 1 P1 0 0 1 1 1 1 0 0 0 P0 0 1 1 0 1 0 0 1
Usually, V = 1 during blanking, however when VBI data is detected and V = 0 is the desired output, set the MRC[3] SAV, EAV V-status of Mode Register C (MRC) to "1".
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PEDL7662-02 Semiconductor Output Data Format MSM7662
CLKX2 HVALID Y[7:0] Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb4
Cr n-4 Y n-3 Cb n-2 Y n-2 Cr n-2 Y n-1
8-bit (YCbCr: 2x clock) Output
CLKX2 CLKO HVALID Y[7:0] C(7:0) Y0 Cb0 Y1 Cr0 Y2 Cb2 Y3 Cr2 Y(n-2) Y(n-1)
Cb(n-2) Cr(n-2)
16-bit (Y: 8-bit, CbCr: 8-bit) Output
CLKX2 CLKO HVALID R[7:0] G[7:0] B[7:0] R0 G0 B0 R1 G1 B1 R2 Cb2 B2 R3 Cr3 B3 R(n-2) G(n-2) B(n-2) R(n-1) G(n-1) B(n-1)
24-bit (R: 8-bit, G: 8-bit, B: 8-bit) Output Note: When a single-speed clock (13.5 MHz, etc.) is input in 16-bit or 24-bit (RGB) output mode, the waveform of CLKX2 changes to a single speed waveform, but the format after that is not changed. 29/62
PEDL7662-02 Semiconductor MSM7662
* Timing when using external field memory Field memory timing in the FM-2 mode, using control signals from the decoder Field memory: MSM51V8222, 2 units are used (Y and C) Four memory control signals are supplied from the decoder, M[4]: RSTW, M[5]: RSTR, M[6]: WE:, and M[7]: RE. NTSC Signal (13.5 MHz)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 hsync_l vsync_l hvalid vvalid odd-even y (7:0) c (7:0) RSTW WE HSYNC_L VSYNC_L HVLID VVALID ODD/EVEN RE RSTR Y (7:0) C (7:0)
NTSC: ODD Field
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 hsync_l vsync_l hvalid vvalid odd-even y (7:0) c (7:0) RSTW WE HSYNC_L VSYNC_L HVLID VVALID ODD/EVEN RE RSTR Y (7:0) C (7:0)
NTSC: EVEN Field 30/62
PEDL7662-02 Semiconductor PAL Signal (13.5 MHz)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 31 32 33 34 35 36 37 38 39 hsync_l vsync_l hvalid vvalid odd-even y (7:0) c (7:0) RSTW WE HSYNC_L VSYNC_L HVLID VVALID ODD/EVEN RE RSTR Y (7:0) C (7:0)
MSM7662
PAL: ODD Field
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 31 32 33 34 35 36 37 38 hsync_l vsync_l hvalid vvalid odd-even y (7:0) c (7:0) RSTW WE HSYNC_L VSYNC_L HVLID VVALID ODD/EVEN RE RSTR Y (7:0) C (7:0)
PAL: EVEN Field
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PEDL7662-02 Semiconductor Horizontal Synchronizing Signal The horizontal synchronizing signal timing is shown below.
Front-porch Y[7:0] Hsync back-porch
MSM7662
HVALID HSYNC_L 60 pixels
Horizontal Timing Relation between Video Mode and Pixel Number (default settings when standard signal is input)
Video Mode NTSC Pixel Type ITURBT.601 Square pixel 4fsc PAL ITURBT.601 Square pixel Pixel Rate (MHz) 13.5 12.272727 14.31818 13.5 14.75 Total Pixels 858 780 910 864 944 Active Pixels 720 640 768 720 768 FrontPorch 16 28 8 12 34 Hsync BackPorch 122 112 134 132 142 HBLK Total 138 140 142 144 176
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PEDL7662-02 Semiconductor Synchronizing Signal Timing (default timing when standard signal is input)
0 HVALID 2T T = 1/13.5 MHz
MSM7662
VVALID
60 pixels HSYNC_L 16 pixels HVALID 138 pixels
0 HSYNC_L
VSYNC_L about 10.4 ms ODD (ODD) ODD (EVEN)
about 21.6 ms
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PEDL7662-02 Semiconductor VBI Data Detection (when a Composite signal is input): STATUS1 Timing VBI data detection results are output from the STATUS1 pin.
Detection level OMR[5:3] 80 to 136 video in
MSM7662
STATUS1 HVALID
HSYNC_L
Y[7:0]
VBI Data Detection (when an S-Video signal is input): STATUS1 Timing VBI data detection results are output from the STATUS1 pin.
Detection level OMR[5:3] 80 to 136 video in
STATUS1 HVALID
HSYNC_L
Y[7:0]
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PEDL7662-02 Semiconductor MSM7662
I2C BUS FORMAT
The I2C-bus interface input format is shown below.
Write Mode
S Slave Addres (W) A Subaddress A Data 0 A ...... Data n A P
Read Mode
S Slave Addres (W) Symbol S Slave Address A Subaddress Data n P Start condition Slave address 1000001X, 8th bit is write signal ["0"] or read signal ["1"] Slave address is set at M[2] pin (pin 89). Acknowledge. Generated by slave Subaddress byte Data to write to address designated by subaddress. Stop condition A Subaddress A S Slave Addres (R) Description A Data 20 A P
As mentioned above, the write operation can be executed from subaddress to subaddress continuously. When the write operation is executed at subaddresses discontinuously, the Acknowledge and Stop condition formats are input repeatedly after Data 0. Data can be read at subaddress 0x20 only. If one of the following matters occurs, the decoder will not return "A" (Acknowledge). * The slave address does not match. * A non-existent subaddress is specified. * The write attribute of a register does not match "X" (read ["1"]/write ["0"] control bit). The input timing is shown below.
SDA SCL
1
2
8
ACK
1
2
8
ACK
1
2
8
ACK
S Start Condition
Slave Address
Sub Address
Data Stop Condition
P
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PEDL7662-02 Semiconductor MSM7662
OPERATING MODE SETTING
There are two types of video mode settings. 1. External pin mode: direct setting from dedicated pins 2. Register setting mode: specification by internal register settings These modes can be switched by the mode register MRA[0]. The reset state (default) is the external pin mode. The following registers can be set in the external pin mode. MRA[7:6] Output mode 00: ITU-RBT.656 (SAV, EAV, blank processing) *01: 8 bit (YCbCr) HSYNC_L and VSYNC_L used for synchronization 10: ITU-RBT.601 16 bit (8 bit Y, 8 bit CbCr) 11: RGB (8 bit R, 8 bit G, 8 bit B) *000: NTSC ITU-RBT.601 13.5 MHz (27.0 MHz) 001: NTSC Square Pixel 12.272727 MHz (24.545454 MHz) 010: NTSC 4fsc 14.31818 MHz (28.63636 MHz) 100: PAL ITU-RBT.601 13.5 MHz (27.0 MHz) 101: PAL Square Pixel 14.75 MHz (29.5 MHz)
MRA[3:1]
Sampling mode
Note:
010: NTSC 4fsc cannot be set externally.
Pin Setting Example NTSC, 27 MHz (ITU-RBT.601), Composite input, 8-bit (YCbCr) Output
Pin name MODE[3] MODE[2] MODE[1] MODE[0] CLKSEL PLLSEL INS[2:0] GAINS[2:0] TEST[2:0] SCAN M[2] M[1] M[0] SLEEP = low = high = low = low = low = low = low = low = low = low = low = low = low = low
Condition
Notes 0 : ITU-RBT.656 01 : 8-bit (YCbCr) 10 : 16-bit (Y + CbCr) 11 : RGB 0 : NTSC 1 : PAL 0 : ITU-RBT.601 1 : Square Pixel 0 : twice the pixel frequency 1 : pixel frequency
Normally set to a low level
: low = 1000001, : high = 1000011 Normally set to a low level 0 : normal operation 1 : sleep operation
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PEDL7662-02 Semiconductor MSM7662
INTERNAL REGISTERS
Register List
Register Function Mode Register A (MRA) Mode Register B (MRB) Mode Register C (MRC) Horizontal Sync Trimmer (HSYT) Sync Threshold Level Adjust (STHR) Horizontal Sync Delay (HSDL) Horizontal Valid Trimmer (HVALT) Vertical Valid Trimmer (VVALT) Luminance Control (LUMC) Sync Separation Level (SSEPL) Chrominance Control (CHRC) ACC Loop Filter Control (ACCLF) Hue Control (HUE) Write Sub/Read address Write Write Write Write Write Write Write Write Write Write Write Write Write 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 20 Data byte D7 D6 D5 D4 D3 D2 D1 D0 MRA7 MRA6 MRA5 MRA4 MRA3 MRA2 MRA1 MRA0 MRB7 MRB6 MRB5 MRB4 MRB3 MRB2 MRB1 MRB0 MRC7 MRC6 MRC5 MRC4 MRC3 MRC2 MRC1 MRC0 HSYT7 HSYT6 HSYT5 HSYT4 HSYT3 HSYT2 HSYT1 HSYT0 STHR7 STHR6 STHR5 STHR4 STHR3 STHR2 STHR1 STHR0 HSDL7 HSDL6 HSDL5 HSDL4 HSDL3 HSDL2 HSDL1 HSDL0 HVALID7 HVALID6 HVALID5 HVALID4 HVALID3 HVALID2 HVALID1 HVALID0 VVALID7 VVALID6 VVALID5 VVALID4 VVALID3 VVALID2 VVALID1 VVALID0 LUMC7 LUMC6 LUMC5 LUMC4 LUMC3 LUMC2 LUMC1 LUMC0 AGCLF7 AGCLF6 AGCLF5 AGCLF4 AGCLF3 AGCLF2 AGCLF1 AGCLF0 SSEPL7 SSEPL6 SSEPL5 SSEPL4 SSEPL3 SSEPL2 SSEPL1 SSEPL0 CHRC7 CHRC6 CHRC5 CHRC4 CHRC3 CHRC2 CHRC1 CHRC0 ACCLF7 ACCLF6 ACCLF5 ACCLF4 ACCLF3 ACCLF2 ACCLF1 ACCLF0 HUE7 HUE6 HUE5 HUE4 HUE3 HUE2 HUE1 HUE0 OPCY7 OPCY6 OPCY5 OPCY4 OPCY3 OPCY2 OPCY1 OPCY0 OPCC7 OPCC6 OPCC5 OPCC4 OPCC3 OPCC2 OPCC1 OPCC0 OMR7 OMR6 OMR5 OMR4 OMR3 OMR2 OMR1 OMR0 ADC17 ADC16 ADC15 ADC14 ADC13 ADC12 ADC11 ADC10 ADC27 ADC26 ADC25 ADC24 ADC23 ADC22 ADC21 ADC20 ADC37 ADC36 ADC35 ADC34 ADC33 ADC32 ADC31 ADC30 ZLD7 ZLD6 ZLD5 ZLD4 ZLD3 ZLD2 ZLD1 ZLD0 STATUS7 STATUS6 STATUS5 STATUS4 STATUS3 STATUS2 STATUS1 STATUS0
AGC/Pedestal Loop Filter Control (AGCLF) Write
Output Phase Control for Data Y (OPCY) Write Output Phase Control for Data C (OPCC) Write Optional Mode Register (OMR) ADC Register (ADC1) ADC Register (ADC2) ADC Register (ADC3) 0 Level Detect Register (ZLD) Stataus Register (STATUS) Write Write Write Write Write Read
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PEDL7662-02 Semiconductor MSM7662
Register Parameters
Registers controlled from the I2C-bus are listed below. An asterisk (*) indicates that the register setting value is the default value.
Mode Register A (MRA)
Register Name Default Recommended Value
Write only

MRA[7] MRA[6] MRA[5] MRA[4] MRA[3] MRA[2] MRA[1] MRA[0] 0 -- 1 -- 0 -- 0 0 0 -- 0 -- 0 -- 0 --
00: ITU-RBT.656 *01: Y, C 8 bits 10: Y, C 16 bits 11: RGB 24 bits Video output mode is selected. MRA[5] Chroma format *0: Offset binary 1: 2's complement MRA[4] Undefined Set to 0 1: S-video input MRA[3:1] Input Sampling mode *000: NTSC ITU-RBT.601 13.5 MHz 001: NTSC Square Pixel 12.272727 MHz 010: NTSC 4fsc 14.31818 MHz 100: PAL ITU-RBT.601 13.5 MHz 101: PAL Square Pixel 14.75 MHz 110, 111: Undefined Sampling rate is selected MRA[0] MODE[3:0] pin select *0: External pin mode 1: Register mode Note: Only the setting of MODE[3:0] is valid in this external pin mode.
MRA[7:6]
Video output mode
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PEDL7662-02 Semiconductor Mode Register B (MRB)
Register Name Default Recommended Value
MSM7662 Write only
MRB[7] MRB[6] MRB[5] MRB[4] MRB[3] MRB[2] MRB[1] MRB[0] 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
*00: FIFO-1 (use internal memory) 01: FIFO-2 (use internal memory) 10: FM-1 (use external memory, external control) 11: FM-2 (use external memory, control signals supplied from M[7:4]) Note: In the FIFO-1 mode, the number of pixels per 1H is output at the standard setting value. In the FIFO-2 mode, the number of pixels per 1H is fixed in accordance with an input H period and output. In the FM-1 and FM-2 modes, a decoded result is output without any changes according to the SYNC signal. A field memory is required externally to output the fixed number of pixels in those modes. In the FM-2 mode, a field memory control signal is output from the pin M[7:4]. MRB[5] Color killer mode *0: Auto color killer (Chrominance signal level is set to "0" if the color burst level is below the specified value.) *1: Forced color killer (Chrominance signal level is forced to "0".) MRB[4] Blue Back 0: OFF (Video signal is demodulated and output regardless of synchronization detection.) *1: AUTO (Blue Back is output when synchronization is not detected.) Note: When Blue Back output is selected, if "H" level is not input during no signal output, a vertical synchronizing signal (VSYNC_L) is not output. MRB[3:2] Clamp mode *00: Analog clamp 01: Analog, Digital hybrid clamp 10: Digital clamp (HSY clamp) 11: Undefined Clamp mode is selected. MRB[1:0] Y/C separation mode *00: Adaptive comb filter (Correlation of 3 lines is monitored and operating mode is selected.) 01: Non-adaptive comb filter (Operating mode is always fixed.) 10: Use trap filter. (Comb filter is not used.) 11: Undefined Note: Adaptive comb filter 2/3-line comb filter for NTSC Comb filter/trap filter for PAL Non-adaptive comb filter 3-line comb filter for NTSC 2-line cosine comb filter for PAL
MRB[7:6]
Synchronization mode
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PEDL7662-02 Semiconductor Mode Register C (MRC)
Register Name Default Recommended Value
MSM7662 Write only
MRC[7] MRC[6] MRC[5] MRC[4] MRC[3] MRC[2] MRC[1] MRC[0] 1 1 0 0 0 -- 0 0 0 -- 0 -- 0 0 0 0
0: Fix *1: Auto Note: This register decides automatically when the sampling frequency of input signals is ITU-RBT.601. MRC[6] Sub pixel alignment *0: Use pixel position compensating circuit. 1: Do not use pixel position compensating circuit. MRC[5] Pixel sampling rate *0: (4:2:2) 1: (4:1:1) MRC[4] Data-pass control *0: Use DECIMATOR at 2x sampling. 1: Do not use DECIMATER. Note: This register is valid when a 2x clock (27 MHz) is input. MRC[3] SAV, EAV V-status *0: During blanking, V = 1 1: During blanking, while VBI data is not detected, V = 1 MRC[2] RGB output level *0: 0 to 255 1: 16 to 235 MRC[1:0] Undefined Set to 0 Horizontal Sync Trimmer (HSYT)
Register Name Default Recommended Value
MRC[7]
NTSC/PAL auto select
Write only

HSYT[7] HSYT[6] HSYT[5] HSYT[4] HSYT[3] HSYT[2] HSYT[1] HSYT[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HSYT[7:4] HSY start trimmer ( 8 pixels) $C to $B (*$0): -4 to +11 (-32 to +88 pixels) HSYT[3:0] HSY stop trimmer ( 8 pixels) $C to $B (*$0): -4 to +11 (-32 to +88 pixels) Note: The HSYT signal provides the clamp timing to the A/D converter during digital clamp or hybrid clamp mode. Because this signal can move to the pedestal position, the pedestal clamp can be used. However, this signal can not be observed from outside. Sync. Threshold level adjust (STHR)
Register Name Default Recommended Value
Write only

STHR[7] STHR[6] STHR[5] STHR[4] STHR[3] STHR[2] STHR[1] STHR[0] 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 1
STHR[7:0] Sync. depth $00 to $FF (*$1E): 0 to 255 Note: The STHR signal changes the HSYNC_L detection level. The numerical unit described here is determined based on 80IRE obtained from doubling the pedestal value of standard signal, if set to 40IRE. For example, the default 0x1E is 30 in digital value, which is reduced to 15IRE.
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PEDL7662-02 Semiconductor MSM7662
Horizontal Sync Delay (HSDL)
Register Name Default Recommended Value
Write only

HSDL[7] HSDL[6] HSDL[5] HSDL[4] HSDL[3] HSDL[2] HSDL[1] HSDL[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HSDL[7:0]
Note:
HSYNC_L delay trimmer ( 1 pixel) $80 to $7F (*$00): -128 to +127 (-128 to +127 pixels) The HSYNC_L sync signal output position is adjusted.
HVALT [4] 0 0 HVALT [3] 0 0 HVALT [2] 0 0 HVALT [1] 0 0 HVALT [0] 0 0
Horizontal Valid Trimmer (HVALT) Write only
Register Name Default Recommended Value HVALT [7] 0 0 HVALT [6] 0 0 HVALT [5] 0 0
HVALT[7:4] HVALID start trimmer ( 2 pixels) $8 to $7 (*$0): -8 to +7 (-16 to +14 pixels) HVALT[3:0] HVALID stop trimmer ( 2 pixels) $8 to $7 (*$0): -8 to +7 (-16 to +14 pixels) Note: HVALID start position and end position are changed.
Vertical Valid Trimmer (VVALT)
Register Name Default Recommended Value VVALT [7] 0 0
Write only
VVALT [6] 0 0 VVALT [5] 0 0

VVALT [4] 0 0 VVALT [3] 0 0 VVALT [2] 0 0 VVALT [1] 0 0 VVALT [0] 0 0
VVALT[7:4] VVALID start trimmer ( 1 line) $8 to $7 (*$0): -8 to +7 VVALT[3:0] VVALID stop trimmer ( 1 line) $8 to $7 (*$0): -8 to +7 Note: VVALID start position and end position are changed.
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PEDL7662-02 Semiconductor MSM7662
Luminance Control (LUMC)
Register Name Default Recommended Value
Write only

LUMC[7] LUMC[6] LUMC[5] LUMC[4] LUMC[3] LUMC[2] LUMC[1] LUMC[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
*0: OFF 1: ON Note: Control range while limiter is ON: 16 to 235 LUMC[6] Use of prefilter *0: Do not use prefilter. 1: Use prefilter. LUMC[5:4] Aperture bandpass select *00: range0 (middle) 01: range1 10: range2 11: range3 (high) LUMC[3:2] Coring range select *00: coring off 01: 4LSB 10: 5LSB 11: 7LSB LUMC[1:0] Aperture filter weighting factor *00: 0.00 01: 0.25 10: 0.75 11: 1.50 Note: These registers are used for contour compensation.
LUMC[7]
Output level limiter
AGC/Pedestal Loop filter control (AGCLF) Write only
Register Name Default Recommended Value

AGCLF AGCLF AGCLF AGCLF AGCLF AGCLF AGCLF AGCLF [7] 0 0 [6] 1 1 [5] 0 0 [4] 0 0 [3] 0 0 [2] 0 0 [1] 0 0 [0] 0 0
AGCLF[7:6] AGC loop filter time constant 00: slow *01: medium 10: fast 11: MGC mode Note: The AGC convergence time is determined. These registers converge about 4 times faster by slow-medium-fast steps. In the MGC mode, the amplification is determined by reference level. AGCLF[5:0] AGC reference level $20 to $1F (*$00): -32 to +31
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PEDL7662-02 Semiconductor MSM7662
Sync separation level (SSEPL) Write only
Register Name Default Recommended Value SSEPL [7] 0 0 SSEPL [6] 0 0 SSEPL [5] 0 0

SSEPL [4] 0 0 SSEPL [3] 0 0 SSEPL [2] 0 0 SSEPL [1] 0 0 SSEPL [0] 0 0
*0: Do not use pedestal clamp. 1: Use pedestal clamp (AGC stops operating). SSEPL[6:0] Sync. separation level $40 to $3F (*$00): -64 to +63 Note: The default setting outputs the pedestal position as a black level. Chrominance Control (CHRC) Write only
Register Name Default Recommended Value
SSEPL[7]
Pedestal Clamp on/off

CHRC[7] CHRC[6] CHRC[5] CHRC[4] CHRC[3] CHRC[2] CHRC[1] CHRC[0] 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1
Set to 0 *0: OFF 1: ON Note: Control range while limiter is ON: 16 to 224 CHRC[2] Chroma bandpass filter 0: OFF *1: ON CHRC[1:0] Color kill threshold factor 00: 0.500 color burst level *01: 0.250 color burst level 10: 0.125 color burst level 11: Color killer off Note: The color killer decision level is selected based upon color burst ratio. ACC Loop filter control (ACCLF) Write only
Register Name Default Recommended Value
CHRC[7:4] CHRC[3]
Undefined C-Output level limiter

ACCLF ACCLF ACCLF ACCLF ACCLF ACCLF ACCLF ACCLF [7] 0 0 [6] 0 0 [5] 1 1 [4] 0 0 [3] 0 0 [2] 0 0 [1] 0 0 [0] 0 0
ACCLF[7] Undefined Set to 0 ACCLF[6:5] ACC loop filter time constant 00: slow *01: medium 10: fast 11: MCC mode Note: The ACC convergence time is determined. These registers converge about 4 times faster by slow-medium-fast steps. In the MCC mode, the amplification is determined by reference level. ACCLF[4:0] ACC reference level $10 to $0F (*$00): -16 to +15 43/62
PEDL7662-02 Semiconductor Hue control (HUE)
Register Name Default Recommended Value
MSM7662 Write only
HUE[7] HUE[6] HUE[5] HUE[4] HUE[3] HUE[2] HUE[1] HUE[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HUE[7:0] Hue control $80 to $7F (*$00): -180 to +178.6 degrees Note: The phase is controlled. It changes about 1.4 degrees per bit.
Output phase control for data Y (OPCY) Write only
Register Name Default Recommended Value

OPCY[7] OPCY[6] OPCY[5] OPCY[4] OPCY[3] OPCY[2] OPCY[1] OPCY[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OPCY[7:2] OPCY[1:0]
Note:
Undefined Set to 0 Output phase control for data Y *00: normal 01: forward l clock 10: backward 2 clock 11: backward l clock The output phase of data Y is controlled.
Output phase control for data C (OPCC) Write only
Register Name Default Recommended Value

OPCC[7] OPCC[6] OPCC[5] OPCC[4] OPCC[3] OPCC[2] OPCC[1] OPCC[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OPCC[7:2] OPCC[1:0]
Note:
Undefined Set to 0 Output phase control for data C *00: normal 01: forward l clock 10: backward 2 clock 11: backward l clock The output phase of data C is controlled.
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PEDL7662-02 Semiconductor Optional Mode Register (OMR) Write only
Register Name Default Recommended Value 0 1 0 1 0 0
MSM7662

1 1 0 0 0 0 0 0 0 0
OMR[7] OMR[6] OMR[5] OMR[4] OMR[3] OMR[2] OMR[1] OMR[0]
HSYNC output timing select *0: HSYNC output signal is detected near sync threshold and sync tip. 1: HSYNC output signal is detected at sync threshold setting position. Note: When the HSYNC output signal is detected at sync threshold setting position, it is hardly affected by noise. OMR[6] VSYNC output timing select *0: VSYNC_L is synchronized to HSYNC_L and then output 1: VSYNC_L is output when a VSYNC input signal is detected. Note: When a non-standard signal is decoded, the output is stabilized after the VSYNC_L input signal is detected (setting 1). OMR[5:3] Multiplex signal detection level (VBID etc.) 000: 80 001: 88 *010: 96 011: 104 100: 112 101: 120 110: 128 111: 136 Note: The levels to detect multiplexed signals sent during the vertical blanking period are set. The result is output from the STATUS[1] pin or STATUS[4] register. OMR[2] Hi-Z output in SLEEP mode *0: Active 1: Hi-Z Note: This register selects either normal or Hi-Z as the output pin status in SLEEP mode. *0: NTSC/PAL identification 1: HLOCK sync detection OMR[0] Status3 output mode *0: TV/VCR identification 1: CSYNC Note: OMR[1:0] correspond to the STATUS[2:3] output of output pins. OMR[1] Status2 output mode
OMR[7]
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PEDL7662-02 Semiconductor ADC register 1 (ADC1)
Register Name Default Recommended Value
MSM7662 Write only
ADC1[7] ADC1[6] ADC1[5] ADC1[4] ADC1[3] ADC1[2] ADC1[1] ADC1[0] 0 0 0 0 0 1 0 1 0 0 0 -- 0 -- 0 --
ADC1[7] ADC1[6] ADC1[5:4]
Video amp select Undefined Clamp current select
ADC1[3] ADC1[2:0]
Undefined ADC input select
*0: Use 1: Do not use Set to 0 *00: 1.0 01: 0.75 10: 0.25 11: 0.1 Set to 0 *000: ADI-VIN1 (composite-1) 001: ADI-VIN2 (composite-2) 010: ADI-VIN3 (composite-3) 011: ADI-VIN4 (composite-4) 100: ADI-VIN5 (composite-5) 101: ADI-VIN1 (Y-1), AD2-VIN5 (C-1) 110: ADI-VIN2 (Y-1), AD2-VIN6 (C-1) 111: Prohibited setting (ADC enters sleep state)
ADC register 2 (ADC2)
Register Name Default Recommended Value
Write only
ADC2[7] ADC2[6] ADC2[5] ADC2[4] ADC2[3] ADC2[2] ADC2[1] ADC2[0] 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0
ADC2[7]
ADC gain control mode select 0: manual *1: auto ADC gain manual select 000: 1.00 *001: 1.35 010: 1.75 011: 2.30 100: 3.00 101: 3.80 110: 5.00 111: Undefined ADC initialize condition gain select 0: not initialize *1: initialize Undefined Set to 0 ADC gain control and stage select 00: 2nd change end 01: 3rd change end *10: 3rd change loop 11: Undefined 46/62
ADC2[6:4]
ADC2[3]
ADC[2] ADC2[1:0]
PEDL7662-02 Semiconductor ADC register 3 (ADC3)
Register Name Default Recommended Value
MSM7662 Write only
ADC3[7] ADC3[6] ADC3[5] ADC3[4] ADC3[3] ADC3[2] ADC3[1] ADC3[0] 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0
Undefined Set to 0 ADC gain control margin level select 000: 10 mV 001: 20 mV *010: 40 mV 011: 80 mV 100: 160 mV ADC3[3] Undefined Set to 0 ADC3[2:0] ADC gain control line select 000: 1 line 001: 2 lines *010: 4 lines 011: 8 lines 100: 16 lines Note: These registers determine the analog gain control decision level. The stability can be obtained from higher values.
ADC3[7] ADC3[6:4]
0 level detect register (ZLD)
Register Name Default Recommended Value ZLD[7] 0 0
Write only
ZLD[6] 0 0 ZLD[5] 0 0

ZLD[4] 0 0 ZLD[3] 0 0 ZLD[2] 0 0 ZLD[1] 1 1 ZLD[0] 0 0
ZLD[7:3] ZLD[2:0]
Note:
Undefined Set to 0 0 level detect width ( 8 pixel) 000: Undefined 001: 8 pixels *010: 16 pixels 011: 24 pixels 100: 32 pixels 101: 40 pixels 110: 48 pixels 111: 56 pixels These registers decide the continuance of sync tip level and its result is reflected in AGC gain. The stability can be obtained from higher values.
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PEDL7662-02 Semiconductor Status register (STATUS)
Register Name Default Recommended Value
MSM7662 Read only
STATUS STATUS STATUS STATUS STATUS STATUS STATUS STATUS [7] -- -- [6] -- -- [5] -- -- [4] -- -- [3] -- -- [2] -- -- [1] -- -- [0] -- --
STATUS[7:5] STATUS[4] STATUS[3] STATUS[2] STATUS[1] STATUS[0]
Undefined VBI interval multiplex signal detection 0: Non-detection, 1: Detection HLOCK sync detection 0: Non-detection, 1: Detection NTSC/PAL identification 0: NTSC, 1: PAL Fifo1/Fifo2 identification Mode Register B (bit 6) 0: Fifo1, 1: Fifo2 FTFO overflow detection 0: Non-detection, 1: Detection
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PEDL7662-02 Semiconductor Relationship between Register Setting Value and Adjusted Value Horizontal Sync Trimmer Position adjustment of sync tip clamp timing signal HSYT [7:4]
Register Setting Value (0x)
MSM7662
:Adjusting the starting position
C D E F 0* 0 1 2 3 4 5 6 7 8 9 A B
Adjusted Value (Pixel) -32 -24 -16 -8
+8 +16 +24 +32 +40 +48 +56 +64 +72 +80 +88
HSYT [3:0]
Register Setting Value (0x)
:Adjusting the end position
C D E F 0* 0 1 2 3 4 5 6 7 8 9 A B
Adjusted Value (Pixel) -32 -24 -16 -8
+8 +16 +24 +32 +40 +48 +56 +64 +72 +80 +88
Horizontal Sync Delay Adjustment of the starting position of horizontal sync signal HSDL [7:0] Unit: [pixel]
Register Setting Value (0x)
MSB[7 : 4] 8 9 A B -80 -79 -78 -77 -76 -75 -74 -73 -72 -71 -70 -69 -68 -67 -66 -65 C -64 -63 -62 -61 -60 -59 -58 -57 -56 -55 -54 -53 -52 -51 -50 -49 D -48 -47 -46 -45 -44 -43 -42 -41 -40 -39 -38 -37 -36 -35 -34 -33 E -32 -31 -30 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 F -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0* 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15 1 +16 +17 +18 +19 +20 +21 +22 +23 +24 +25 +26 +27 +28 +29 +30 +31 2 +32 +33 +34 +35 +36 +37 +38 +39 +40 +41 +42 +43 +44 +45 +46 +47 3 +48 +49 +50 +51 +52 +53 +54 +55 +56 +57 +58 +59 +60 +61 +62 +63 4 +64 +65 +66 +67 +68 +69 +70 +71 +72 +73 +74 +75 +76 +77 +78 +79 5 +80 +81 +82 +83 6 7 +96 +112 +97 +113 +98 +114 +99 +115
0* -128 -112 -96 1 2 3 4 5 6 LSB [3 : 0] 7 8 9 A B C D E F -127 -111 -95 -126 -110 -94 -125 -109 -93 -124 -108 -92 -123 -107 -91 -122 -106 -90 -121 -105 -89 -120 -104 -88 -119 -103 -87 -118 -102 -86 -117 -101 -85 -116 -100 -84 -115 -99 -114 -98 -113 -97 -83 -82 -81
+84 +100 +116 +85 +101 +117 +86 +102 +118 +87 +103 +119 +88 +104 +120 +89 +105 +121 +90 +106 +122 +91 +107 +123 +92 +108 +124 +93 +109 +125 +94 +110 +126 +95 +111 +127
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PEDL7662-02 Semiconductor Horizontal Valid Trimmer Position adjustment of horizontal valid pixel timing signal HVALT [7:4]
Register Setting Value (0x)
MSM7662
:Adjusting the starting position
8 9 A B C D -6 E -4 F -2 0* 0 1 +2 2 +4 3 +6 4 5 6 7 +8 +10 +12 +14
Adjusted Value (Pixel) -16 -14 -12 -10 -8
HVALT [3:0]
Register Setting Value (0x)
:Adjusting the end position
8 9 A B C D -6 E -4 F -2 0* 0 1 +2 2 +4 3 +6 4 5 6 7 +8 +10 +12 +14
Adjusted Value (Pixel) -16 -14 -12 -10 -8
Vertical Valid Trimmer Position adjustment of vertical valid line timing signal VVALT [7:4]
Register Setting Value (0x)
:Adjusting the starting position
8 -8 9 -7 A -6 B -5 C -4 D -3 E -2 F -1 0* 0 1 +1 2 +2 3 +3 4 +4 5 +5 6 +6 7 +7
Adjusted Value (Line)
VVALT [3:0]
Register Setting Value (0x)
:Adjusting the end position
8 -8 9 -7 A -6 B -5 C -4 D -3 E -2 F -1 0* 0 1 +1 2 +2 3 +3 4 +4 5 +5 6 +6 7 +7
Adjusted Value (Line)
AGC Loop Filter Control AGCLF [5:0] :Adjusting AGC sync level
Unit: [IRE], Default: 40 IRE
Register Setting Value (0x)
MSB [5 : 4] 2 -32 -31 -30 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 3 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0* 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15 1 +16 +17 +18 +19 +20 +21 +22 +23 +24 +25 +26 +27 +28 +29 +30 +31
0* 1 2 3 4 5 6 LSB [3 : 0] 7 8 9 A B C D E F
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PEDL7662-02 Semiconductor Sync Separation Level SSEPL [6:0] :Adjusting the blanking level MSM7662
Unit: [IRE], Default: 40 IRE
Register Setting Value (0x)
MSB [6 : 4] 4 -64 -63 -62 -61 -60 -59 -58 -57 -56 -55 -54 -53 -52 -51 -50 -49 5 -48 -47 -46 -45 -44 -43 -42 -41 -40 -39 -38 -37 -36 -35 -34 -33 6 -32 -31 -30 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 7 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0* 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15 1 +16 +17 +18 +19 +20 +21 +22 +23 +24 +25 +26 +27 +28 +29 +30 +31 2 +32 +33 +34 +35 +36 +37 +38 +39 +40 +41 +42 +43 +44 +45 +46 +47 3 +48 +49 +50 +51 +52 +53 +54 +55 +56 +57 +58 +59 +60 +61 +62 +63
0* 1 2 3 4 5 6 LSB [3 : 0] 7 8 9 A B C D E F
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PEDL7662-02 Semiconductor ACC Loop Filter Control ACCLF [4:0] :Adjusting the color burst level MSM7662
Unit: [IRE], Default: 40 IRE
Register Setting Value (0x)
MSB [4] 1 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0* 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15
0* 1 2 3 4 5 6 LSB [3 : 0] 7 8 9 A B C D E F
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PEDL7662-02 Semiconductor Hue Control Adjustment of color subcarrier phase HUE [7:0] Unit: [degree]
Register Setting Value (0x)
MSM7662
MSB [7 : 4] 8 9 A B C D E F 0* 1 2 3 4 5 6 7
0* -180.0 -157.5 -135.0 -112.5 -90.0 -67.5 -45.0 -22.5 +0.0 +22.5 +45.0 +67.5 +90.0 +112.5 +135.0 +157.5 1 2 3 4 5 6 LSB [3 : 0] 7 8 9
-178.6 -156.1 -133.6 -111.1 -88.6 -66.1 -43.6 -21.1 +1.4 +23.9 +46.4 +68.9 +91.4 +113.9 +136.4 +158.9 -177.2 -154.7 -132.2 -109.7 -87.2 -64.7 -42.2 -19.7 +2.8 +25.3 +47.8 +70.3 +92.8 +115.3 +137.8 +160.3 -175.8 -153.3 -130.8 -108.3 -85.8 -63.3 -40.8 -18.3 +4.2 +26.7 +49.2 +71.7 +94.2 +116.7 +139.2 +161.7 -174.4 -151.9 -129.4 -106.9 -84.4 -61.9 -39.4 -16.9 +5.6 +28.1 +50.6 +73.1 +95.6 +118.1 +140.6 +163.1 -173.0 -150.5 -128.0 -105.5 -83.0 -60.5 -38.0 -15.5 +7.0 +29.5 +52.0 +74.5 +97.0 +119.5 +142.0 +164.5 -171.6 -149.1 -126.6 -104.1 -81.6 -59.1 -36.6 -14.1 +8.4 +30.9 +53.4 +75.9 +98.4 +120.9 +143.4 +165.9 -170.2 -147.7 -125.2 -102.7 -80.2 -57.7 -35.2 -12.7 +9.8 +32.3 +54.8 +77.3 +99.8 +122.3 +144.8 +167.3 -168.8 -146.3 -123.8 -101.3 -78.8 -56.3 -33.8 -11.3 +11.3 +33.8 +56.3 +78.8 +101.3 +123.8 +146.3 +168.8 -167.3 -144.8 -122.3 -99.8 -77.3 -54.8 -32.3 -9.8 +12.7 +35.2 +57.7 +80.2 +102.7 +125.2 +147.7 +170.2
A -165.9 -143.4 -120.9 -98.4 -75.9 -53.4 -30.9 -8.4 +14.1 +36.6 +59.1 +81.6 +104.1 +126.6 +149.1 +171.6 B -164.5 -142.0 -119.5 -97.0 -74.5 -52.0 -29.5 -7.0 +15.5 +38.0 +60.5 +83.0 +105.5 +128.0 +150.5 +173.0 C -163.1 -140.6 -118.1 -95.6 -73.1 -50.6 -28.1 -5.6 +16.9 +39.4 +61.9 +84.4 +106.9 +129.4 +151.9 +174.4 D -161.7 -139.2 -116.7 -94.2 -71.7 -49.2 -26.7 -4.2 +18.3 +40.8 +63.3 +85.8 +108.3 +130.8 +153.3 +175.8 E F
-160.3 -137.8 -115.3 -92.8 -70.3 -47.8 -25.3 -2.8 +19.7 +42.2 +64.7 +87.2 +109.7 +132.2 +154.7 +177.2 -158.9 -136.4 -113.9 -91.4 -68.9 -46.4 -23.9 -1.4 +21.1 +43.6 +66.1 +88.6 +111.1 +133.6 +156.1 +178.6
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PEDL7662-02 Semiconductor Sync. Threshold Level Adjust Adjustment of the detection threshold of horizontal sync signal SHTR [7:0] Unit: [IRE]/2
Register Setting Value (0x)
MSM7662
MSB [7 : 4] 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1* 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 2 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 3 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 4 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 5 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 6 96 97 98 99 7 8 9 A B C D E F 112 128 144 160 176 192 208 224 240 113 129 145 161 177 193 209 225 241 114 130 146 162 178 194 210 226 242 115 131 147 163 179 195 211 227 243
0 1 2 3 4 5 6 LSB [3 : 0] 7 8 9 A B C D E* F
100 116 132 148 164 180 196 212 228 244 101 117 133 149 165 181 197 213 229 245 102 118 134 150 166 182 198 214 230 246 103 119 135 151 167 183 199 215 231 247 104 120 136 152 168 184 200 216 232 248 105 121 137 153 169 185 201 217 233 249 106 122 138 154 170 186 202 218 234 250 107 123 139 155 171 187 203 219 235 251 108 124 140 156 172 188 204 220 236 252 109 125 141 157 173 189 205 221 237 253 110 126 142 158 174 190 206 222 238 254 111 127 143 159 175 191 207 223 239 255
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PEDL7662-02 Semiconductor MSM7662
Filter Characteristics
Band Pass Filter (NTSC ITU-RBT.601)
0
-20
Level [dB]
-40
-60
-80
-100 0 1 2 3 4 5 6 Frequency [MHz]
Band Pass Filter (PAL ITU-RBT.601)
0
-20
Level [dB]
-40
-60
-80
-100 0 1 2 3 4 5 6 Frequency [MHz]
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PEDL7662-02 Semiconductor MSM7662
Trap Filter (NTSC ITU-RBT.601)
0
-20
Level [dB]
-40
-60
-80
-100 0 1 2 3 4 5 6 Frequency [MHz]
Trap Filter (PAL ITU-RBT.601)
0
-20
Level [dB]
-40
-60
-80
-100 0 1 2 3 4 5 6 Frequency [MHz]
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PEDL7662-02 Semiconductor MSM7662
Pre Filter
0
-20
Level [dB]
-40
-60
-80
-100 0 1 2 3 4 5 6 Frequency [MHz]
Sharp Filter
0
-20
Level [dB]
-40
-60
-80
-100 0 1 2 3 4 5 6 Frequency [MHz]
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PEDL7662-02 Semiconductor MSM7662
Decimation Filter
0
-20
Level [dB]
-40
-60
-80
-100 0 2 4 6 8 10 12 Frequency [MHz]
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PEDL7662-02 Semiconductor MSM7662
BASIC APPLICATION CIRCUIT EXAMPLES
1) Application Circuit for FIFO-1 and FIFO-2 Modes
3.3 V or 5 V 4.7 kW Video in (Composite Y input) 75 W I2C Controller 4.7 kW 1000 pF 1000 pF 1000 pF 47 mF 47 mF 47 mF
1 mF 75 W 4 10 mF 10 mF 10 kW
SDA SCL RESET_L AVDD VIN(1:4) VRT1 AMPOUT LPF ADIN1 CLPOUT1 VRCL1
DAVDD
DVDD Y(7:0) C(7:0) B(7:0) Video LSI
1 mF Video in (C input) 75 W 75 W 1 mF 10 mF 2
VRB1
MSM7662
10 mF
VIN(5:6) VRT2 AMPOUT2 LPF ADIN2 1 mF CLPOUT2 VRB2 AGND DAGND DGND MODE[3:0]
HVALID VVALID ODD HSYNC_L VSYNC_L CLKX2O CLKXO CLKX2 OSC
AMPOUT
LPF ADIN 250 pF
100 W
* Connect the M7662 decoder and a video LSI device according to the output interface (ITURBT.656, 8-bit [YCbCr], 16-bit [YCbCr], RGB). * Video input can be four composite inputs or two S-Video inputs. * Connect unused video input pins to AGND. If a composite signal is input, the C input side (video amp, A/D converter, etc.) will be in the OFF operation state. * If the input is limited by the composite signal, connect VIN (5:6), VRT2, VRB2, AMPOUT2, ADIN2, and CLPOUT2 pins to AGND. Externally attached components such as capacitors may be removed. * Set the MODE[3:0] pins to the prescribed setting. * Supply power and GND for analog, A/D, and digital circuits on the circuit board should be separated at the power source wherever possible. Power and GND lines for analog and A/D circuits must be wide and low impedance.
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PEDL7662-02 Semiconductor 2) Application Circuit for FM-1 and FM-2 Modes
3.3 V or 5 V 4.7 kW Video in (Composite Y input) 1 mF 75 W 4 75 W 10 mF 10 mF 10 kW 1 mF Video in (C input)75 W 75 W 1 mF 10 mF 2 I2 C Controller 4.7 kW 1000 pF 1000 pF 1000 pF 47 mF 47 mF 47 mF Memory control signal
MSM7662
SDA SCL RESET_L AVDD VIN(1:4) VRT1 AMPOUT LPF ADIN1 CLPOUT1 VRCL1 VRB1
DAVDD
DVDD
M[7:4] Y(7:0) C(7:0) B(7:0)
Field memory Field memory Video LSI
MSM7662
10 mF
VIN(5:6) VRT2 AMPOUT2 LPF ADIN2 1 mF CLPOUT2 VRB2 AGND DAGND DGND MODE[3:0]
CLKXO HVALID VVALID ODD HSYNC_L VSYNC_L CLKX2O CLKX2 OSC
AMPOUT
LPF ADIN 250 pF
100 W
* Select either 16-bit [YCbCr] or RGB output as the output interface. * Number of field memories utilized 16-bit [YCbCr]: Use 2 field memories. RGB: Use 3 field memories. * Video input can be four composite inputs or two S-Video inputs. * Connect unused video input pins to AGND. If a composite signal is input, the C input side (video amp, A/D converter, etc.) will be in the OFF operation state. * If the input is limited by the composite signal, connect VIN (5:6), VRT2, VRB2, AMPOUT2, ADIN2, and CLPOUT2 pins to AGND. Externally attached components such as capacitors may be removed. * Set the MODE[3:0] pins to the prescribed setting. * For the FM-1 mode setting, externally generate and supply control signals for the field memory. * For the FM-2 mode setting, memory control signals from M[7:4] can be supplied to the field memory. * For the FM-2 mode setting, the output timing for HSYNC_L, VSYNC_L, ODD, VVALID, and HVALID becomes the memory read timing. Data output from memory is aligned with the various sync signal timings. (See page 30 and page 31) * Supply power and GND for analog, A/D, and digital circuits on the circuit board should be separated at the power source wherever possible. Power and GND lines for analog and A/D circuits must be wide and low impedance. 60/62
PEDL7662-02 Semiconductor MSM7662
PACKAGE DIMENSIONS
(Unit : mm)
TQFP100-P-1414-0.50-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.55 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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PEDL7662-02 Semiconductor MSM7662
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
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Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
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